One or more embodiments of the present invention pertain to method and apparatus for checking integrated circuit (IC) designs.
As the size of integrated circuit (IC) features continues to shrink, and the demand for increased circuit density has correspondingly increased, IC designers have been turning to automated design tools, layout tools, and checking tools. Fabrication of ICs is dependent upon the creation of a set of xe2x80x9cmasksxe2x80x9d used during fabrication, where each mask in the set represents a different step in the fabrication (typically an addition or deletion of material). A digitized representation of an image of a mask is commonly called a xe2x80x9cmask layerxe2x80x9d or simply a xe2x80x9clayerxe2x80x9d. Each layer is comprised of a set of geometric shapes representing the desired configuration of materials such as metal, polysilicon, or substrate in a finished IC. For example, layers can represent the deposition of metal, or the etching away of resistive material between two layers of metal so that a xe2x80x9cviaxe2x80x9d is opened.
As is well known, semiconductor physical design follows design rules that are defined, for example, by an integrated circuit manufacturing factory (for example, a foundry) to fabricate the design using a particular manufacturing technology. Thus, design rules are restrictions, or guidelines, within which the design can be implemented so the foundry can use its manufacturing technology to fabricate ICs according to the design. In general, before a layout design of a particular level is transferred onto a photolithography reticle, the design is in the form of a digital computer file, where each of the features has a plurality of associated X and Y coordinates that define their location on a mask. A key task in designing a quality IC is to ensure that the designed features obey the design rules and electrical rules (for example, rules specifying connectivity). For example, and without limitation, design rule checks may identify: (a) layers having a floating metal; (b) devices having a partial gate; (c) metal features with a width larger than a predetermined amount; (d) violations of width, spacing, enclosure, and hole design rules; (e) violations of slot rules; (f) violations of dead zone rules; and (g) special gate rules. Accordingly, because ICs typically comprise a large number of features, designers typically employ commercially available software products to perform operations known as xe2x80x9cdesign rule checksxe2x80x9d (DRCs) and/or xe2x80x9celectrical rule checksxe2x80x9d (ERCs). In general, one or more DRCs/ERCs are applied to the features of each layer: (a) directly by measuring their shapes and their relationships to each other, and/or (b) indirectly by creating intermediate layers (also known as xe2x80x9cderived layersxe2x80x9d). Exemplary DRC/ERC processing may include determinations of whether certain minimum interfeature spacings have been violated, whether successive levels are overlapping, and so forth. Derived layers often are more amenable to design rule checking than the original layers, and can be used in the creation of subsequently derived layers.
As is known, a physical computer aided design (xe2x80x9cCADxe2x80x9d) environment is set upxe2x80x94based on design rules and electrical rulesxe2x80x94to implement an IC design, and to check whether the design meets the design and electrical rules. For high performance CPU chip designs, a large number of complex DRCs/ERCs are performed, each of the complex DRCs/ERCs requires a large amount of computer time to complete (for example, some of the DRCs/ERCs are so complex that merely completing one such check may require many steps of sizing and stretching features to separate those features that violate the DRCs/ERCs from those that do not). In addition, the complex DRCs/ERCs typically are performed on each feature in a category of featuresxe2x80x94even though only a small percentage of features in the category of features might violate the complex DRCs/ERCs. Since a typical design database for a complex IC contains many features, every extra step in a rules check weighs heavily on the overall performance of the verification software. In fact, at times, the verification software can run out of memory or disk space.
In light of the above, there is a need to simplify DRCs/ERCs for complex IC designs.
One or more embodiments of the present invention advantageously satisfy the above-identified need in the art. Specifically, one embodiment of the present invention is a method for checking integrated circuit design files using rules files. Each of the rules files has a rule associated therewith. The rules are sequentially compared with objects associated with the design files in an object-to-check-pool (OTCP). The sequence in which the rules are compared to objects in the OTCP is arranged to maximize a probability of determining whether design characteristics of the objects in the OTCP satisfies all rules associated with the rules files while minimizing a number of rules that must be compared with the OTCP.